Modern semiconductor electronic device packages such as integrated circuit (IC) chips are formed on a wafer by building multiple stacked layers of materials and components on a semiconductor substrate. A single wafer will contain a plurality of individual ICs or dies, which are later separated following fabrication by a cutting process referred to in the art as singulation or dicing. The semiconductor devices typically incorporate numerous electrically active components which are formed in multiple layers of an electrically insulating or dielectric material. Metal conductor interconnects, which may be made of copper in some embodiments, are formed by various additive patterning and deposition processes such as damascene and dual damascene to electrically couple the active components together in the various layers and to create circuit paths or traces within a single layer of dielectric material. Modern semiconductor fabrication entails a repetitive sequence of process steps including material deposition (conductive and non-conductive dielectric materials), photolithographic patterning of circuits in the dielectric material, and material removal such as etching and ashing which gradually build the stacked semiconductor device structures.
Some of the foregoing semiconductor processing steps used in fabricating semiconductors specifically include oxidation, diffusion, doping, annealing, and chemical vapor deposition (CVD). These processes are typically performed at elevated temperatures within heated controlled environments. CVD is a chemical vapor deposition process used to produce or deposit thin films of material on the wafer including without limitation metals, silicon dioxide, tungsten, silicon nitride, silicon oxynitride, and various dielectrics. The CVD process entails placing a wafer or plurality of wafers in a heated reaction chamber and introducing one or more reactant gases into the chamber. The gases contain with various chemical precursors (e.g. SiH2C12 and NH3 or silane and NH3 to form a silicon nitride film) that react at the heated wafer surface to form a thin film of the desired semiconductor material and thickness thereon. The uniformity of the film deposited on the wafer by CVD is affected and controlled by regulating and attempting to optimize CVD process parameters such as temperature of the wafer, reaction chamber pressure, flow path and rate of reactant gases, and deposition time or duration.
One type of heated or thermal reaction chamber used in CVD processes are vertical semiconductor furnaces. These vertical furnaces are capable of holding a plurality of vertically-stacked semiconductor wafers which undergo CVD batch processing simultaneously. The vertical furnaces include a thermal reaction vessel or chamber which may be loaded with multiple wafers that in some embodiments are held in a vertically-stackable rack referred to in the art as a wafer ladder or boat. The wafer boat comprises a frame having multiple horizontal slots which each hold an individual wafer in spaced-apart, stacked vertical relationship to the other wafers. The wafer boats may typically hold from approximately 50-125 wafers. Vertical space is provided between the wafers to allow the CVD reactant gases to circulate therethrough for forming the desired material film deposits on top of the wafers. The thermal reaction chambers are commonly cylindrical in shape (also referred to as reaction tubes) and generally have a closed top and open bottom to allow for insertion of the wafer boats holding the vertical wafer stacks.
The thermal reaction chambers, wafer boats or racks, and other components that may be exposed to the heat and corrosive gases are commonly made of quartz or SiC to withstand CVD process temperatures that may range from about 200-1200 degrees C. in some applications depending on the type of semiconductor material film to be deposited on the wafers.
The wafer boats may be disposed on an openable/closeable lid assembly which forms a bottom closure and platform for supporting the wafer boat. The lid assembly is configured and adapted to temporarily attach to and seal the bottom of the reaction chamber to form a gas-tight temporary connection during CVD processing. The lid assembly may be mounted on a vertical elevator or lift which is operable to raise and lower the wafer boat into and from the reaction chamber. The reaction chamber and associated assembly typically includes a gas manifold with gas inlets and gas outlets for introducing and removing CVD process reactant gases from the reaction chamber. A means for rotating the wafer boat and wafers held therein when the boat is positioned in the reaction chamber may be provided to promote uniform gas flow and heating throughout the wafer stack.
Some examples of conventional vertical semiconductor furnaces and associated appurtenances are shown in U.S. Pat. Nos. 6,538,237; 6,435,865; 6,187,102; 6,031,205; and 7,241,701; all of which are incorporated herein by reference in their entireties.
The vertical semiconductor furnaces include a heat source, which in some embodiments may include resistance type heaters, radiant type heaters, or a combination thereof. Examples of resistance type heaters include electric resistive wire coil elements or similar. Some examples of radiant type heaters include heating lamps or quartz-heating elements. The heaters are typically disposed outside but proximate to the quartz reaction chamber to heat the chamber and increase its internal temperature.
In order to improve manufacturing efficiencies and reduce production costs, wafer sizes have steadily increased over the years. Standard silicon wafer sizes have steadily grown from about 200 mm (about 8 inches diameter) to 300 mm (about 12 inches diameter). The next generation wafer standard has been set for 450 mm (about 18 inches in diameter). The next generation wafer size of 450 mm has created a challenge in maintaining a uniform temperature in the vertical wafer stacks throughout the wafer boat during the CVD process that is desired to promote uniform material film deposition on each wafer's surface.
Existing heater arrangements used in CVD thermal reaction chambers have proven to be inadequate to provide the needed uniformity in temperature for maintaining the desired consistency in both material film thickness deposited over the entire surface of each individual wafer, and from wafer-to-wafer throughout the entire batch or stack of wafers being processed for the larger next generation wafer sizes. Ideally, each wafer in the entire batch of wafers undergoing CVD in the thermal reaction chamber should have a uniform film thickness in order to meet acceptable process thickness variation tolerances on an individual wafer and wafer-to-wafer basis. Some existing heater arrangements used for traditionally smaller 200-300 mm diameter wafers do not provide the necessary temperature control and uniformity to maintain the desired tolerances for 450 mm wafers. Horizontal temperature variation between the edges and center of the wafers cause generally unacceptable variances in layer thicknesses deposited on each wafer. Temperatures at the wafer center are typically lower than at the edges. Vertical temperature variations in the stack of wafers held by the wafer boat cause generally unacceptable variances in layer thicknesses deposited from wafer-to-wafer in the stack.
An improved heater arrangement for vertical semiconductor furnaces is desired to meet the challenges of the next generation wafer size.